The pursuit of making computing systems more faster and more power efficient has led to advancement in interface communications to improve throughput without increasing, while ideally reducing, energy consumption. Often, as clock speeds increase, a desire to increase data transition times on interface busses to match the faster clock speeds exists. Future double data rate (DDR) dynamic random-access memory (DRAM) performance targets will soon exceed DRAM transistor switching capabilities.
Although not observed in the context of memory systems, some computing systems have implemented multi-level (e.g., more than two levels) signaling architectures to increase throughput over an interface bus. However, a challenge with multilevel signaling in high speed, high bandwidth, low power memory systems is non-idealities that negatively affect system performance, for example, with regards to signal voltage levels and signal voltage margins. An example is the inability of signal drivers to fully drive the voltage levels of the multilevel signals to a high supply voltage or to a low supply voltage within a data period due to non-ideal performance of the circuits (e.g., pull-up and pull-down transistors) of the signal drivers. Variations in power, temperature, and fabrication process may further degrade system performance. As a result, the voltage range for the multilevel signals is reduced, which decreases the voltage margins for the different voltage levels. More generally, the signal drivers may be unable to adequately drive the multilevel signals to the correct voltage levels, which may result in data errors.